31:41

Verilog Tip 23: sequential logic circuit description using Vivado

21:44

Verilog Tip 22: Combinational Logic description using Vivado

08:32

Verilog Tip 21: Verilog 2001

16:23

Verilog Tip 20: FSM

06:28

Verilog Tip 19: BCD cnt

05:39

Verilog Tip 18: cascadible counter

04:39

Verilog Tip 17: counter

04:51

Verilog Tip 16: testbench

08:50

Verilog Tip 15. Latch inference 피하기

05:59

Verilog Tip 14: Latch vs FF

04:02

Verilog Tips 13: non blocking assignment

05:41

Verilog Tips #12 continuous vs. procedural assignment

05:15

Verilog Tip #11constant

06:18

Verilog Tip 8: multiple bit signal

01:50

Verilog Tip 10: Verilog vector port declaration

03:49

Verilog Tip 9: Verilog memory (array)

08:34

Verilog Tip 7: signal type

05:22

Verilog Tip 6: Verilog module port type rule

02:51

Verilog Tip 5: module port declaration 방법들

09:35

Verilog Tip 4: module port connection 표기 방식

06:27

Verilog Tip 3: port, net, instance

06:45

Verilog Tip 2: module basic

02:03

Verilog Tip 1: module 이란?

01:01

소은고택 가는길 (퇴로마을입구에서)

25:38

전산전자공학 논문작성법 3부

21:10

전산전자공학 논문작성법 2부

20:59

공학 논문작성법 1부

19:55

한동대 홍보영상 2000년

16:21

불멍

00:33

고택에서 비오는 날 낙수물

02:14

밀양 소은고택

07:01

2 4 Zedboard BNNPYNQ

07:26

2 3 Board Test 2 Inference

09:43

2 2 HLS Programming 2 practice part

10:57

2 1 Deep Learning Training 1 tutorial part

12:36

2 1 Deep Learning Training 2 practice part

24:13

2 2 HLS Programming 1 tutorial part

06:34

1 3 PYNQ Tutorial pynq os setting

13:15

1 2 HLS programming

08:21

2 3 Board Test 1 BNN Settings

19:42

1 1 Pynq Tutorial

47:28

Verilog 9

34:47

Verilog 7

26:40

verilog 8

11:49

Verilog 6

01:28:17

교교특강 (4차산업혁명과 SW인재)

47:28

Verilog 9

52:20

Verilog 12

27:36

Verilog 11

37:03

Verilog 10

27:53

Verilog-14

23:24

Verilog 15

07:56

Verilog 13

20:55

verilog 3

33:37

verilog 5

25:34

verilog 2

18:57

verilog 4

39:24

verilog 1

01:02

비오는 날 청록의 숲속

19:17

Tinkercad 사용법 (논리회로)