Computer Organisation and Architecture [KTU Syllabus Based]
84 videos • 105,590 views • by Namitha Ramachandran
Basic Computer Organisation and Architecture concepts, KTU Syllabus based.
1
Computer Architecture and Organization 1
Namitha Ramachandran
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2
Basic operational concepts-Part 1 2
Namitha Ramachandran
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3
Basic Operational Concepts -part 2 3
Namitha Ramachandran
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4
Basic operational concepts part 3 4
Namitha Ramachandran
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5
Bus structure 5
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6
Memory Locations and Addresses 6
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7
Memory locations and addressing part-2 7
Namitha Ramachandran
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8
Memory locations and addresses part-3 8
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9
Instruction execution and straight line sequencing part 1 9
Namitha Ramachandran
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10
Instruction execution and stright line sequencing part 2 10
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11
INSTRUCTION EXECUTION AND STRAIGHT LINE SEQUENCING PART 2 EDITED
Namitha Ramachandran
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12
Adressing modes part 1 11
Namitha Ramachandran
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13
Addressing mode part 2 12
Namitha Ramachandran
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14
Addressing modes part 3 13
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15
Addressing modes part 4 14
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16
Addressing mode part 5 15
Namitha Ramachandran
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17
SUBROUTINES AND STACK part 1 16
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18
subroutine and stack part 2 17
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19
BASIC I/O OPERATIONS 18
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20
ADVANCED RISC MACHINES (ARM) -ARCHITECTURE basics only 19
Namitha Ramachandran
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21
MODULE 2: Basic Processing Unit -part1 20
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22
Performing an Arithmetic or Logic Operation 21
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23
Execution of complete instruction 22
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24
unsigned multiplication 23
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25
Signed Multiplication 24
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26
BOOTH MULTIPLICATION ALGORITHM 25
Namitha Ramachandran
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27
BOOTH ALGORITHM -EXAMPLE 26
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28
INTEGER DIVISION -Restoring division algorithm for unsigned numbers 27
Namitha Ramachandran
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29
NON RESTORING DIVISION ALGORITHM 28
Namitha Ramachandran
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30
FLOATING POINT NUMBER REPRESENTATION 29
Namitha Ramachandran
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31
FLOATING POINT MULTIPLICATION AND DIVISION ALGORITHMS 30
Namitha Ramachandran
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32
PREVIOUS YEAR UNIVERSITY QUESTIONS 31
Namitha Ramachandran
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33
MODULE 3 STARTING-I/O ORGANIZATION 32
Namitha Ramachandran
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34
PROCESSOR I/O SYNCHRONIZATION MECHANISM-VECTORED INTERRUPT 33
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35
DIRECT MEMORY ACCESS 34
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36
BUSES 35
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37
INTERFACE CIRCUITS 36
Namitha Ramachandran
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38
STANDARD I/O INTERFACES -PCI BUS 37
Namitha Ramachandran
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39
UNIVERSAL SERIAL BUS INTERFACE 38
Namitha Ramachandran
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40
MODULE 4-MEMORY SYSTEM BASIC CONCEPTS 39
Namitha Ramachandran
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41
SEMICONDUCTOR RAM MEMORY ORGANIZATION 40
Namitha Ramachandran
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42
STATIC RAM --SRAMs edited 41
Namitha Ramachandran
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43
DYNAMIC RAM -PART 1 42
Namitha Ramachandran
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44
DRAM PART 2 43
Namitha Ramachandran
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45
MEMORY SYSTEM CONSIDERATION 44
Namitha Ramachandran
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46
SEMICONDUCTOR ROM MEMORIES 45
Namitha Ramachandran
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47
SEMICONDUCTOR MEMORY ORGANISATION ( SOLUTION FOR UNIVERSITY QUESTION -MODULE 4 )
Namitha Ramachandran
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48
COMPARISON SPEED ,COST AND SIZE OF RAMs AND ROMs 46
Namitha Ramachandran
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49
CACHE MEMORY OPERATIONS -BASICS edited 47
Namitha Ramachandran
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50
CACHE MAPPING FUNCTIONS -PART1 48
Namitha Ramachandran
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51
CACHE MAPPING FUNCTIONS -PART2 49
Namitha Ramachandran
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52
CACHE MAPPING BASICS -Simplified 49 edited
Namitha Ramachandran
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53
DIRECT MAPPING -Simplified
Namitha Ramachandran
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54
ASSOCIATIVE MAPPING -Simplified edited 49
Namitha Ramachandran
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55
SET ASSOCIATIVE MAPPING -Simplified edited 49
Namitha Ramachandran
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56
LRU- CACHE REPLACEMENT ALGORITHM 50
Namitha Ramachandran
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57
CACHE MAPPING PROBLEM SOLVING
Namitha Ramachandran
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58
ASSOCIATIVE CACHE MAPPING-PROBLEM SOLVING
Namitha Ramachandran
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59
PROCESSOR LOGIC DESIGN-PART 1 51
Namitha Ramachandran
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60
REGISTER TRANSFER using common BUS & MEMORY TRANSFER LOGIC 52
Namitha Ramachandran
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61
UNIVERSITY QUESTION SOLVED 67
Namitha Ramachandran
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62
PROCESSOR LOGIC DESIGN WITH COMMON BUS SYSTEM AND USING SCRATCH PAD MEMORY SYSTEM 53
Namitha Ramachandran
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63
ACCUMULATOR REGISTER 54
Namitha Ramachandran
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64
ARITHMETIC LOGIC UNIT DESIGN -PART 1 55
Namitha Ramachandran
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65
MODULE 5 :UNIVERSITY QUESTION AND ANSWER
Namitha Ramachandran
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66
MODULE 5 UNIVERSITY QUESTION & ANSWER
Namitha Ramachandran
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67
MODULE 5 UNIVERSITY QUESTION & ANSWER
Namitha Ramachandran
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68
EFFECT OF OUTPUT CARRY IN ARITHMETIC CIRCUIT 56
Namitha Ramachandran
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69
ARITHMETIC AND LOGIC CIRCUIT DESIGN
Namitha Ramachandran
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70
STATUS REGISTER 57
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71
DESIGN OF SHIFTER 58
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72
PROCESSOR LOGIC 59
Namitha Ramachandran
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73
DESIGN OF ACCUMULATOR REGISTER
Namitha Ramachandran
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74
CONTROL LOGIC DESIGN INTRODUCTION -edited
Namitha Ramachandran
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75
CONTROL LOGIC DESIGN FOR SIGNED MAGNITUDE ADDITION/SUBTRACTION 61
Namitha Ramachandran
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76
MICROPROGRAM CONTROL ORGANIZATION 62
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77
CONTROL OF PROCESSOR UNIT 63
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78
TYPES OF MICROINSTRUCTIONS 64
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79
MICROPROGRAM SEQUENCER 66
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80
ARITHMETIC AND LOGIC CIRCUIT DESIGN
Namitha Ramachandran
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81
MICROPROGRAM SEQUENCER
Namitha Ramachandran
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82
MICROPROGRAMMED COMPUTER ORGANISATION
Namitha Ramachandran
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83
HORIZONTAL & VERTICAL MICROINSTRUCTIONS
Namitha Ramachandran
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84
COA Solving University question
Namitha Ramachandran
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