VLSI design solved question paper May 15
35 videos • 13,226 views • by in5minutes
1
Module2_Vid59_Worst Case designing equivalent to symmetric inverter (part 4)
in5minutes
Download
2
Module2_Vid58_Worst Case designing equivalent to symmetric inverter (part 3)
in5minutes
Download
3
Module2_Vid56_Worst Case designing equivalent to symmetric inverter (Part 1)
in5minutes
Download
4
Module2_Vid57_Worst Case designing equivalent to symmetic inverter (part 2)
in5minutes
Download
5
Module3_Vid67_SR, D, JK FlipFlop implementation in static, pseudo nmos, dynamic ccmos style (Part 2)
in5minutes
Download
6
Module3_Vid66_SR, D and JK Flip Flop implementation in static style [Part 1]
in5minutes
Download
7
Module4_Vid15_Sizing of SRAM (E) transistor for Read and Write operation (part 3).
in5minutes
Download
8
Module4_Vid14_Sizing of SRAM (E) transistor for Read and Write operation (part 2)
in5minutes
Download
9
Module4_Vid13_Sizing of SRAM (E) transistor for Read and Write operation (part 1)
in5minutes
Download
10
Module1_Vid12_Short Channel Effect - Velocity Saturation and Mobile Degradation (part 3)
in5minutes
Download
11
Module1_Vid11_Short Channel Effect - Velocity Saturation and Mobility Degradation (part 2)
in5minutes
Download
12
Module1_Vid10_Short Channel Effect - Velocity Saturation and Mobility Degradation (part 1)
in5minutes
Download
13
Module4_Vid68_Row Decoder implementation at transistor level (Part 2)
in5minutes
Download
14
Module4_Vid67_Row Decoder implementation at transistor level (Part 1)
in5minutes
Download
15
Module2_Vid50_Problem on Propagation delay (part 2)
in5minutes
Download
16
Module2_Vid49_Problem on Propagation delay (part 1)
in5minutes
Download
17
Power Dissipation Static part2
in5minutes
Download
18
Module3_Vid65_JKlatch implementation in all styles static, dynamic, pseudo NMOS, CCMOS (part 2)
in5minutes
Download
19
Module3_Vid64_JK latch implementation in all styles static, dynamic, pseudo NMOS, CCMOS (part 1)
in5minutes
Download
20
Module3_Vid18_Implementation of Expression Static,Pseudo,Dynamic,Clocked Cmos
in5minutes
Download
21
Module3_Vid7_Implementation of 2 Input Nor Static,Pseudo,Dynamic,Clocked Cmos (part 1)
in5minutes
Download
22
fabrication nwell process part 3
in5minutes
Download
23
fabrication nwell process part 2
in5minutes
Download
24
fabrication nwell process part 1
in5minutes
Download
25
Module4_VId54_EPROM, EEPPROM, FLASH MEMORIES FLOATING (part 3)
in5minutes
Download
26
Module4_VId53_EPROM, EEPPROM, FLASH MEMORIES FLOATING (part 2)
in5minutes
Download
27
Module4_VId55_EPROM, EEPPROM, FLASH MEMORIES FLOATING (part 4)
in5minutes
Download
28
Module6_Vid_30_Dynamic Power Dissipation Part 2
in5minutes
Download
29
Module2_Vid28_CMOS Inverter Critical Voltage Problem
in5minutes
Download
30
Module3_Vid4_cmos 2 input nand in static, pseudo, dynamic and clocked cmos style
in5minutes
Download
31
Module6_Vid_46_Basics of Power Distribution
in5minutes
Download
32
Module5_Vid_46_Array Multiplier21ns Part 1
in5minutes
Download
33
Module6_Vid_52_4 * 4 Barrel Shifter Part 3
in5minutes
Download
34
nand part2
in5minutes
Download
35
nand part1
in5minutes
Download