22:41

Live Interactive Timing Constraints Setup

09:01

Unit 9, RTL2Routing, Reading timing constraints. Part 3/3

14:16

Unit 8, RTL2Routing, Reading Timing Constraints, Part 2/3

11:24

Unit 7 - RTL2Routing, Reading timing constraints, Part 1/3

10:34

Topic 12, TCL Series, Dealing with Collections, Part 2/2

09:27

Topic 11, TCL Series, Dealing with Collections - part 1/2

05:31

Topic 10, TCL Series, Regsub

08:47

Topic 9, TCL Series, Regexp - Regular Expressions

14:15

Unit 6 - RTL2Routing, Design Read (Part 2/2)

04:16

Topic 8, TCL Series, File Read & Write

08:21

Topic 7, TCL Series , Procedures

06:14

Topic 6, TCL Series, Operators

06:45

Topic 5, TCL Series, Loops

09:16

Topic 4, TCL Series, Control Flow (If-else, Switch)

06:34

Topic #3, TCL Series, Key difference between “”, {}, []

08:50

Topic #2, TCL Series, Data Types

07:29

Topic #1, TCL Series, Variables

12:08

Unit 5 - RTL2Routing, Design Read (part 1/2)

18:48

Unit 4, RTL2Routing, TCL Series Part 1

11:57

Unit 3, RTL2Routing, Design Library Setup (Part 2/2)

23:12

Unit 2, RTL2Routing, Design Library Setup (Part 1/2)

07:57

Unit 1: RTL2Routing, Introduction

13:36

PD Topic #42: Latch Timing, Part 6: Analyzing LATCH based timing reports; Scenario 4 of Latch usage

09:23

PD Topic #41: Latch Timing, Part 5 – Using Latches to have Glitch-Free Clock Gating

05:52

PD Topic #40: Latch Timing Series Part 4 – Using Lockup Latches to Fix Hold Issues

06:18

PD Topic #39: Latch Timing, Part 3 – Fixing Negative Slack in Flip-Flop Timing Paths with Latches

06:29

PD Topic #38: Latch Timing Part 2 – Latches vs. Flip-Flops: Key Advantages, Challenges

29:11

PD Topic #37 Latch Timing: What makes Setup and Hold Time time of a Latch/Flip-Flops

11:09

PD Topic #36: Handling Asynchronous Clocks & Data Transfers | Synchronizers Explained

06:34

PD Topic #35: Multi-Cycle Paths for Slow-to-Fast Clock Timing (Part 2) | Setup & Hold MCP

15:07

PD Topic #34: Multi-Cycle Paths - Fast to Slow Synchronous Clocks | Setup & Hold MCP

09:50

PD Topic #33: Introducing Multi-Cycle Timing for Setup and Hold | Timing Exceptions Explained

05:47

PD Topic #32: Importance of the -master Option in create_generated_clock

14:08

PD Topic #31: Defining Clocks in Physical Design | Master & Generated Clocks Explained

18:24

PD Topic #30: Semi-Custom Global Clock Tree Implementation Across Partitions

09:27

PD Topic #29: Clock Tree Synthesis (CTS) - Building the H-Tree & Flow Integration

18:09

PD Topic #28: Clock Tree Synthesis (CTS) - Why It’s Essential for Clock Distribution

10:27

PD Topic #27: Designing a Divide-by-3 Circuit | Clock Division & Duty Cycle Adjustment

10:42

PD Topic #26: Clock Generation & Distribution | Oscillator, PLL, and Frequency Division Explained

07:51

PD Topic #25: Phases of Clock Distribution | From Input to Die to End Flops

08:15

PD Topic #24: Introduction to Clock Distribution & Upcoming Topics on Clocks

15:41

PD Topic #23: Timing Report Analysis | Input, Output & Feedthrough Paths Explained

14:12

PD Topic #22: Timing Report Analysis (Part 3) | Capture Path, Required Time & Slack

14:36

PD Topic #21: Timing Report Analysis (Part 2) | Launch Part, Delays & Transition Times

15:15

PD Topic #20: Reading a Timing Report (Part 1) | Understanding Path Groups in STA

11:41

PD Topic #19: Constraining an Output Path | Output Delay, Virtual Clock (Part 4/4)

10:08

PD Topic #18: Constraining an Input Path | Input Delay, Virtual Clock, Part 3/4

15:18

PD Topic #17: Checking Timing Constraints on a Flop-to-Flop Path (Part 2/4)

10:07

PD Topic #16: How to Check if a Timing Path is Constrained (Part 1/4)

15:07

PD Topic #15: Key Design Objects in Physical Design | Cells, Pins, Ports, Nets

00:36

Download Notes of PD Videos Topic 1-14

18:11

PD Topic #14: Understanding Timing Paths & Slack | Required Time vs. Arrival Time

11:10

PD Topic #13: Recap & Understanding Timing Arcs in STA

11:53

PD Topic #12: Introduction to Static Timing Analysis | Ensuring Setup & Hold Time at Endpoints

13:12

PD Topic #11: Understanding Power in Standard Cell Library | Leakage, Switching & Internal Power

15:53

PD Topic #10: Timing Content of Standard Cell Library | Delay and Transition Lookup Tables

12:19

PD Topic #9: Exploring Standard Cell Libraries | Common part, Cell as driver & receiver

12:07

PD Topic #8: Understanding Standard Cells in Physical Design

07:26

PD Topic #7: Evaluating Netlist Optimization at the Synthesis Stage | Tips for QoR Improvement

12:21

PD Topic #6: Final Stages of Synthesis | Optimization, Database Writing & Reporting Explained